1. Field of the Invention
This invention relates to trench-type MOSFETs and more specifically to a structure and process for shrinking the mesa width in a trench device.
2. Description of the Related Art
Referring to FIG. 1, a typical trench type, vertical conduction power MOSFET 10 includes a plurality of trenches 12 formed in semiconductor body 14. Semiconductor body 14 is usually a silicon die that includes an epitaxially grown silicon layer (epitaxial silicon layer) 16 of one conductivity (e.g. N-type in FIG. 1) formed over a silicon substrate 18 of the same conductivity, the epitaxial silicon layer 16 having a lower concentration of impurities than the silicon substrate 18. A channel region 20 (sometimes referred to as body region) is formed in epitaxial silicon layer 16 and extends from the top surface of the semiconductor body to a first depth. Channel region 20 has a conductivity opposite to that of epitaxial layer 16 (e.g. P-type in FIG. 1). Formed within channel region 20 are source regions 22, which have the same conductivity (e.g. N-type in FIG. 1) as epitaxial silicon layer 16.
As is well known, trenches 12 extend to a depth below the depth of channel region 20 and include gate insulation 24, which may be formed of silicon dioxide, on at least the sidewalls of trenches 12. The bottom of each trench 12 is also insulated with silicon dioxide or the like and a gate electrode 26 is disposed within each trench 12. Gate electrodes 26 may be composed of conductive polysilicon. As is illustrated in FIG. 1, gate electrodes 26 are recessed to a position below the top of the trenches and, thus, below the top surface of the semiconductor body.
A typical trench type power MOSFET further includes a source electrode 28, which is electrically connected to source regions 22, and a high conductivity contact region 30, which is also formed in channel region 20. High conductivity contact region 30 is highly doped with dopants of the same conductivity as channel region 20 (e.g. P-type in FIG. 1) in order to reduce the contact resistance between source contact 28 and channel region 20. In addition, dielectric caps 32, which conveniently may be made of tetraethylorthosilicate (TEOS) insulation, electrically isolate the gate electrodes 26 from the source electrode 28. A typical trench type power MOSFET 10 further includes a drain electrode 33 in electrical contact with silicon substrate 18.
It is well known that the density of the current that a power MOSFET may carry is directly proportional to the number of formed channels per unit area. One way of increasing the number of such formed channels is to reduce the spacing between or pitch of the trenches. Reduction in pitch of the trenches is, however, limited by the minimum width of the mesa, which is the top surface of the die between adjacent trenches, shown as 34 on FIG. 1. The minimum width of the mesa is defined by source regions 22 and high conductivity regions 30 and the source contact area, namely, the contact area between the source electrode 28 and the source region 22.